1. Field of the Invention
The present invention relates to a frequency dividing phase shift circuit, and more particularly to a frequency dividing phase shift circuit which is applied to a receiver to output 4-phase output signals different in phase by 90 degrees one after another.
2. Description of the Related Art
There are known communication apparatuses using an ISM (industrial, scientific and medical) radio band, a radio band for a specific small power communication and the like. In recent years, miniaturization and low power consumption are demanded in the communication apparatus, and many functions provided therein are subjected to IC implementation. More specifically, the IC implementation of circuits such as an LNA, Mixer, IF filter, oscillator, PLL frequency synthesizer, and demodulator in a receiver is advanced. Particularly, in a receiver mainly used for a remote keyless entry (RKE) and a tire pneumatic pressure monitoring system (TPMS), it is preferably possible to receive an electromagnetic wave signal in a 315 MHz band, a 434 MHz band and an 868 MHz band by using the same IC, so as to deal with adjustable to various domestic and foreign specifications. Furthermore, an IF frequency band is shifted from a conventional 10.7 MHz band to a few hundred kHz in accordance with incorporation of the IF filter, in which an IRM (Information Rights Management) capable of removing an image signal is required.
In order to realize the receiver as described above, a ⅙ frequency dividing phase shift circuit is necessary for a 315 MHz band, a ¼ frequency dividing phase shift circuit for a 434 MHz band, and a ½ frequency dividing phase shift circuit for an 868 MHz band, in which 4-phase signals can be outputted.
Generally, a ½n (n is a natural number) frequency dividing phase shift circuit performs frequency division on a signal having the frequency of about 1.8 GHz and generated by an oscillator, and generates the 4-phase signals shifted by 90 degrees one after another. The ½n frequency dividing phase shift circuit is generally realized by a ½(n−1) frequency dividing circuit for outputting a signal having the duty of 50%, and a 4-phase signal output circuit. The ½(n−1) frequency dividing circuit is provided with gate-type D-type flip-flop circuits of (n−1) stages, and the 4-phase signal output circuit is provided with a D-type flip-flop circuit of one stage. However, in case of the ⅙ frequency dividing phase shift circuit, if a ⅓ frequency dividing circuit and the 4-phase signal output circuit are simply combined, 4-phase signals having phases different by 90 degrees one after another cannot be outputted because the duty of output of the ⅓ frequency dividing circuit is not 50%. Accordingly, a circuit configuration is complicated to realize the ⅙ frequency dividing phase shift circuit for outputting the 4-phase signals.
As a conventional frequency dividing phase shift circuits, a chrominance subcarrier signal generating apparatus is disclosed in Japanese Patent No. 2,816,675 (first conventional example), in which a chrominance subcarrier signal having different phases is outputted for balanced modulation of two color difference signals.
FIG. 1 shows the configuration of a frequency dividing phase shift circuit described in the first conventional example. This frequency dividing phase shift circuit includes a first frequency dividing circuit 101 for ⅓ frequency division, a second frequency dividing circuit 102 for ½ frequency division, an NAND circuit 109, and a latch circuit 106.
The first frequency dividing circuit 101 is provided with gate type D-type flip-flop circuits 103 and 104, AND circuits 107 and 108, and an inverter circuit 110. The second frequency dividing circuit 102 is provided with a gate type D-type flip-flop circuit 105. The latch circuit 106 is composed of a gate type D-type flip-flop circuit.
As an external input signal, a chrominance subcarrier signal 6 fsc having six times of a frequency is supplied to the inverter circuit 110 and the NAND circuit 109. An output of the inverter circuit 110 is supplied to a clock input C of the gate-type D-type flip-flop circuit 103 and a clock input C of the gate-type D-type flip-flop circuit 104. An output Q of the gate-type D-type flip-flop circuit 103 is supplied to the AND circuit 108 and the NAND circuit 109. An inversion output Q− of the gate-type D-type flip-flop circuit 103 is supplied to the AND circuit 107. An inversion output Q− of the gate-type D-type flip-flop circuit 104 is supplied to a clock input C of the gate-type D-type flip-flop circuit 105, the AND circuit 108 and the AND circuit 107. An output of the AND circuit 107 is supplied to a data input D of the gate-type D-type flip-flop circuit 103. An output of the AND circuit 108 is supplied to a data input. D of the gate-type D-type flip-flop circuit 104. An inversion output Q− of the gate-type D-type flip-flop circuit 105 is supplied to a data input D thereof. The gate-type D-type flip-flop circuit 105 provides an output Q thereof as a first chrominance subcarrier signal fsc. An output Q of the gate-type D-type flip-flop circuit 105 is supplied to a data input D of the latch circuit 106. An output of the NAND circuit 109 is inverted and supplied to a clock input C of the latch circuit 106. The latch circuit 106 provides an output M thereof as a second chrominance subcarrier signal fsc⊥.
Each of the gate-type D-type flip-flop circuits 103, 104 and 105 latches the data input D in response to a falling edge of a signal supplied to the clock input C. As a result, the output Q and the inversion output Q− in the preceding state are held as the output Q and the inversion output Q− of the gate-type D-type flip-flop circuit.
FIGS. 2A to 2G are timing charts showing an operation of the frequency dividing phase shift circuit described in the first conventional example. In the first frequency dividing circuit 101, the data input of the circuit 103 as the output of the AND circuit 107 is delayed by 120 degrees and outputted as the output Q and the inversion output Q−, as shown in FIG. 2C by a. Also, the data input of the circuit 104 as the output of the AND circuit 108 is delayed by 120 degrees and outputted as the output Q and the inversion output Q−, as shown in FIG. 2D by b. The gate-type D-type flip-flop circuit 105 in the second frequency dividing circuit 102 frequency-divides the signal b into a half. Thus, the ⅙ frequency division signal or first chrominance subcarrier signal fsc is obtained. Also, by using the clock signal 6 fsc, the gate-type D-type flip-flop circuit 106 generates the second chrominance subcarrier signal fsc⊥ from first chrominance subcarrier signal fsc.
However, the frequency dividing phase shift circuit described in the first conventional example is provided with the gate-type D-type flip-flop circuits for three stages, the latch circuit for one stage, the inverter circuit for one stage, and the AND circuits for three stages with the NAND circuit for one stage. Therefore, a circuit is complex with a large number of the circuit elements. As a result, it is not suitable for implementing low current consumption and reduction of a chip layout.